1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device of MIS (metal insulator semiconductor) type with high speed and high integration density.
2. Description of the Prior Art
The integration density of integrated circuits is ccontinuously increasing. Especially, ultra LSIs are being studied and developed. In order to increase the integration density of the integrated circuits, the elements which constitute an integrated circuit must be made small. However, when an MOS transistor is made small, especially when the channel length thereof is shortened, a short channel effect occurs, extremely decreasing the threshold voltage of the transistor. This effect occurs due to extension of a depletion layer into a channel region so that the charge of the channel region is greatly influenced by the drain voltage as well as the gate voltage.
In order to prevent the short channel effect, an impurity is ion-implanted in the channel region to increase the impurity concentration of the channel region to avoid extension of the depletion layer. Alternatively, the thickness of the gate oxide film is made small to increase the influence of an electric field of the gate electrode. Furthermore, it is possible to prevent extension of the depletion layer into the channel region by making the diffusion depth (Xj) of the source and drain regions small enough to prevent the short channel effect. However, when the diffusion depth (Xj) is made small, the resistivities of the source region, the drain region, and the interconnection layer constituted by the diffusion layer increases, because source, drain and interconnection layer are usually formed simultaneously by forming diffused layers. Further, the reduction of the interconnection layer width due to the scaling-down of devices increases the total resistance of interconnect. Therefore, the operation speed of the circuit is extremely reduced. When a shallow p-n junction is formed and the extension of the depletion layer ihto the channel region is controlled, the reverse breakdown voltage of the drain p-n junction is reduced due to so-called "surface breakdown", so that a power supply voltage cannot be increased.